1. Field of the Invention
The present invention relates to a method for controlling an analog/digital converter (hereinafter called A/D converter), specifically, an A/D converter formed as a semiconductor integrated circuit on a semiconductor substrate.
2. Description of the Prior Art
FIG. 38 shows a block diagram of a successive approximation type A/D converter controlled by a conventional control method, which is disclosed, for example, in Japanese Patent Application JP A 1-321728.
The reference numeral 1 denotes a capacitor, 2 is an inverter. The capacitor 1 and the inverter 2 form a chopper type comparator. 3 is a successive approximation register for storing outputs of the comparator, the output of the comparator is called COMP hereinafter. Reference numeral 4 denotes ladder resistors connected in series. 5, 6 on both end of the ladder resistors are input terminals for imposing a standard voltage, which corresponds to the maximum input voltage that the A/D converter can convert. A switch group 7 selects a reference voltage VREF from the divided voltages by the ladder resistors 4, corresponding to the output data of the successive approximation register 3. The ladder resistors 4 and the switch group 7 form a digital/analog converter for converting the digital output of the successive approximation register 3 to an analog voltage signal. Reference numeral 8 denotes an input terminal for inputting an input voltage VIN.
Reference numerals 9, 10, 11 denote semiconductor switches, respectively. The reference voltage VREF output by the switch group 7 is imposed to the capacitor 1 through a semiconductor switch 9. The input voltage VIN inputted from the input terminal 8 is imposed to the capacitor 1 through a semiconductor switch 10. The input side and the output side of the inverter 2 are electrically connected or cut off by a semiconductor switch 11.
Reference numeral 12 is an A/D clock generating block, which generates timing clock signals (hereinafter called signals TZ) for controlling the timing of the turning-on and turning-off of the semiconductor switches 9-11, and the timing of the signal delivery from the successive approximation register 3 to the switch group 7. The A/D clock generating block is not explicitly referred in JP A 1-321728.
The control of the A/D converter is explained below.
FIG. 39 shows a timing chart of the signals in the A/D converter shown in FIG. 38, which is controlled by a conventional method for controlling an A/D converter. In this case, the input voltage VIN inputted from the input terminal 8 is 0.3125 times of the standard voltage, and is converted to a four bit digital signal. In the following explanation, the standard voltage is assumed to be one volt.
At first, a timing signal from the A/D clock generating block 12 makes the semiconductor switch 9 turn off. At the moment when the signal TZ sent from the A/D clock generating block 12 to the successive approximation register 3 changes to HIGH level (hereinafter simply referred "H" or "1"), the digital data stored in the successive approximation register 3 is sent to the switch group 7. The register 3 is designed so that the first output is always a hexadecimal "8h" signal. The output signal controls the switch group 7 to select a switch to output a half of the standard voltage V, because "8h" in the hexadecimal is a half of "16h". As a result, the switch group 7 outputs a reference voltage VREF of 0.5 volts.
Next, the A/D clock generating block 12 sends a signal to turn on the semiconductor switch 11, so that voltages of the input side and output side of the inverter 2 become equal. The value of the equal voltage is determined by the input and output characteristics of the inverter 2. Next, the semiconductor switch 10 is turned on so that the input voltage VIN charges the capacitor 1. After charging the capacitor, the semiconductor switches 10 and 11 are turned off successively. When the signal TZ becomes LOW level (hereinafter simply referred to as "L" or "0"), the semiconductor switch 9 is turned on. While the semiconductor switch 9 is on, the reference voltage VREF is imposed to the capacitor 1 through the switch group 7, and the reference voltage VREF and the input voltage VIN are compared to each other.
When the input voltage VIN is larger than the reference voltage VREF, the inverter 2 outputs "0", and when the input voltage VIN is smaller than the reference voltage VREF, the inverter 2 outputs "1". In this case the input voltage VIN is 0.3125V, and the reference voltage VREF is 1/2 V, thus the output signal COMP of the inverter 2 is "0", which is sent to the successive approximation register 3 and is stored in its register. Namely the value of the most upper bit is identified to be "0".
Then, the timing signal from the A/D clock generating block 12 controls the semiconductor switch 9 to turn off again. When the signal TZ becomes "H", the digital data stored in the successive approximation register 3 is sent to the switch group 7. As a result, since VIN&lt;0.5 Volts, the switch group 7 selects 1/4 volts, which is one fourth of the standard voltage, as a reference voltage VREF, from the outputs of the ladder resistors 7, corresponding to the digital signal. Next, the semiconductor switch 11 is controlled to turn on so that the input and output sides of the inverter 2 are electrically connected. Then the semiconductor switch 11 is made turn on to charge the capacitor 1.
After that, the semiconductor switch 9 is turned on and the reference voltage VREF is imposed from the switch group 7 to the capacitor 1. Then the reference voltage is compared with the input voltage VIN. In this case, the input voltage VIN is 0.3125 volt, and the reference voltage VREF is 1/4 volt, namely the input voltage VIN is larger than the reference voltage VREF, thus the output COMP of the inverter 1 is "1", which is sent to the successive approximation register 3 to be stored therein. The value of the second bit is determined to be "1"in this procedure.
The similar procedures are repeated for the identifying lower bits. The input voltage VIN (0.3125 volt) is successively compared with the reference voltage VREF, which is 3/8 (=0/2+1/4+1/8) volts in the third procedure and is 5/16 (=0/2+1/4+0/8+1/15) volts in the fourth procedure. The outputs COMP at the third and fourth procedures are "0" and "1", respectively, which are sent to the successive approximation register 3 and stored therein.
The signal TZ from the A/D clock generating block 12 is explained below.
FIG. 40 shows a block diagram of an A/D clock generating block 12. A clock signal CK, which is the source clock signal of the A/D converter, is frequency divided by a frequency divider 101 to supply a clock signal CK' to an A/D control signal generating circuit 102. The A/D control signal generating circuit 102, which is controlled by the signal CK', generates a control signal TZ to supply to the successive approximation register 3.
FIG. 32 shows an example the frequency dividing circuit 101. The ENABLE signal in the figure is a signal to actuate the A/D converter. When this signal becomes "H", the A/D converter begins its operation. The frequency dividing circuit 101 generates the control signal CK', by dividing the clock signal CK, and sends it to the A/D control signal generating circuit 102. The A/D control signal generating circuit 102 is provided with two sets of latch A 103 and latch C 104, as shown in FIG. 33.
FIG. 34 and FIG. 35 show an example of the circuit of the latch A 103 and the latch C 104, respectively, which generate the signal TZ. FIG. 41 is a timing chart of signals in the A/D clock generating block 12, showing how the signal TZ is generated.
While the ENABLE signal is "L", the A/D converter is not actuated. When the ENABLE signal turns to "H" in the time section T1 shown in FIG. 39, the A/D converter begins its procedure. According to the signal CK', signals at the points a,b,c,d,e in FIG. 33 are obtained. The timing clock signal TZ is the inverse of the signal at the point a. The A/D converter is controlled by this timing clock signal TZ, which has a constant period.
The successive approximation register 3 in FIG. 38 is explained below.
The successive approximation register 3 is controlled by the control signal TZ from the A/D clock generating block 12. FIG. 36 shows a block diagram of an example of the successive approximation register 3. The successive approximation register 3 comprises four shift registers, four latches 107 for storing the data of the COMP signal, and four output portions 108 for outputting the data in the latches 107 according to a read signal READ. The shift registers are comprised of a shift register 105 for the first bit, and three shift registers A 106 for the lower bits. The shift register 105 and the shift registers A 106 output control signals 1S-4S to the latches 107. The control signals 1S-4S determine a latch 107 in which the COMP signal shall be stored. The output portions 108 read out the data stored in the latch 107, according to the read signal READ, and provide them onto the data bus.
FIG. 37 shows a time chart of outputs of the shift registers 105 and 106. The bit latch control signals 1S-4S, which are outputs of the shift registers 105, 106, become "H" successively. Each latch 107 corresponds to one of the shift registers 105, 106. A shift register which is in the state "H" enables the corresponding latch to store and to latch a signal.
There are many other documents which disclose common methods for controlling a successive approximation type A/D converter. JP A 2-159814 discloses an idea to selectively adjust the TURN ON periods of the input switches in order to improve the preciseness of the A/D conversion. JP A8-288847 discloses an idea to set the initial charging time independently from the comparison period in order to improve the speed of A/D conversion. JP A 6-120828 discloses an idea to change the time constant of the charging of the capacitor in order to shorten the time for A/D conversion. JP A 9-321624 discloses an idea to previously charge the capacitor in order to speed up the A/D conversion. JP A 64-65928 and JP A 62-298230 disclose switching comparators.
The conventional method for controlling an A/D converter uses a clock signal TZ having a constant period for controlling the semiconductor switches 9-11 and the seccessive approximation register 3. The time required for the A/D conversion is mainly determined by the bit number multiplied by the sum of the longest charging time and the longest comparison time. In the charging of the capacitor by the input voltage VIN, the first charging is the longest charging time. On the other hand, when the difference between the former reference voltage and the present reference voltage increases, the time required for the stabilization of the reference voltage is longer. Thus the longest comparison period is a result of the larger difference of the reference voltages.
In the case that the reference voltage is generated using ladder resistors 4, for example, 10 bits 1:8 type A/D converter, the stabilization of the reference voltage requires a long time, when the reference voltage for higher bits is changed to that for lower bits. And for the other steps, long time is not required. However, in the common methods for controlling an A/D converter, the control signal for the semiconductor switches 9-11 and the control signal TZ for the successive approximation register 3 are clock signals with a constant period. As has been mentioned, in general, the A/D conversion time is determined by the longest charging time and the longest comparison time. Thus, in the common method for controlling an A/D converter, there is a lot of wasted time.
In order to shorten A/D conversion time, many ideas are proposed: for example, the speeding up of the response of the chopper amplifier, the use of a higher frequency for the source clock, the use of lower resistance ladder resistors, the use of a smaller capacitance for the capacitor, and the use of a plurality of comparators.
However each of the above entails the following drawbacks.
When the response speed of the chopper amplifier is made higher so as to shorten the conversion time, the size of the transistors must be large, this leads to a larger consumption of the electric power.
Also a chopper amplifier with higher response speed is sensitive, thus it has a tendency to be influenced by noises. In order to reduce the influence of the noises, the configuration of the layout pattern or the structure of the electric circuit shall be changed to use a larger area in the substrate. When a larger area is used, noises generated by the circuit become larger, and the consumption of the electric power also increases. Moreover the increase of the consumption of electric power requires an increase of the width of the lead lines, this leads to an increase in layout pattern area, in turn.
In a successive approximation type A/D converter, the frequency of the clock oscillation cannot be made higher than the frequency corresponding to the charging time. Thus there is a limit for increasing the frequency.
When the resistance of the ladder resistors 4 is made smaller for reducing the converting time, the current in the ladder resistors increases, this leads to an increase in consumption of the electric power.
There is a limit to miniaturization technology to reduce the capacitance of the capacitor (capacitor 1 in FIG. 38) in the chopper amplifier, and the influence of the stray capacitances cannot be neglected.
Use of a plurality of comparators for shortening the comparison time demands an increase in layout area and an increase in the consumption of electric power. Additionally, a matching between the comparators is required, and a complex controller for them is necessary.